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IBM and Samsung have teased a new vertical transistor design “breakthrough” they reckon could transform the semiconductor industry and give Moore’s Law a few years’ more life.

The companies hailed the vertical transistor design as a major benefit to smartphones because it could reduce energy use by 85% compared to finite or fin field-effect transistors (finFET) used in today’s chips.

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As ever-smaller chips become more densely packed with transistors, engineers are running out of space, according to IBM. This physical constraint is blocking the trajectory of integrated circuit chip progress under Moore’s Law, which assumed chip density will double every two years.

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The new vertical design, called Vertical Transport Field Effect Transistors (VTFET) positions transistors perpendicular to the chip rather than horizontally across a wafer in layers, so electric currents flow vertically rather than laterally through the transistors. VTFET gives engineers a chance to pack more transistors in a given space than with FinFET. IBM reckons VTFET has the potential to keep Moore’s Law alive for “years to come”.

The vertical design was developed by IBM Research and Samsung through IBM’s Albany Research Alliance.

“This new approach addresses scaling barriers by relaxing physical constraints on transistor gate length, spacer thickness, and contact size so that these features can each be optimized; either for performance or energy consumption,” IBM Research says in a blogpost.

VTFET continues IBM’s push towards small chip designs and follows its announcement in May of a 2nm chip design. Its test 2nm chip can fit 50 billion transistors in the size of a fingernail. IBM created its 5nm chip in 2017.

The element that limits the number of transistors that can be packed on a FinFET chip is the physical space occupied by spacers, gates and contacts. The Contacted Gate Pitch (CGP) is where components fit.

IBM and Samsung showed they could use “larger source/drain contacts to increase the current on the device.” They could also adjust the gate length to optimize device drive current and leakage, while spacer thickness can be independently tweaked for lower capacitance, according to IBM Research.

“By orienting electrical current flow vertically, the gates, spaces and contacts are no longer constrained in traditional ways: We have room to scale CGP while maintaining healthy transistor, contact, and isolation size,” IBM Research explains in a blogpost.

Other potential energy saving applications could be intensive computing operations such as cryptomining and data encryption. IBM also sees it being used to extend the life of low-energy edge computers that make up the Internet of Things.

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